Name
Abstract | ||
|---|---|---|
We describe an algorithm for the synthesis and optimization of interface circuits for embedded system components such as microprocessors, memory ASIC, and network subsystems with fixed interfaces. The algorithm accepts the timing characteristics of two system components as input, and generates a combinational interface (glue logic) circuit. The algorithm consists of two parts. In the first part, we determine the direct pin-to-pin connections in the interface circuit employing a 0/1 ILP formulation to minimize wiring area and dynamic power consumption. In the second part, we determine logic subcircuits in the interface circuit, utilizing the timing diagrams of the system components. The proposed algorithm has been implemented in a software package SYNTERFACE. Experimental results are presented to demonstrate the effectiveness of the algorithm. |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1145/244522.244852 | ICCAD |
Keywords | Field | DocType |
combinational interface,timing characteristic,logic subcircuits,interface circuit,embedded system component,optimization,system-level design issues,system component,proposed algorithm,glue logic,algorithm,timing diagram,interface synthesis,fixed interface,system-level interface circuit,system level design,application specific integrated circuits,real time systems,embedded system | Computer science,Logic optimization,Interface circuits,Algorithm,Glue logic,Electronic engineering,Application-specific integrated circuit,Software,Dynamic demand,Register-transfer level,System level | Conference |
ISSN | ISBN | Citations |
1063-6757 | 0-8186-7597-7 | 8 |
PageRank | References | Authors |
0.77 | 5 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ki-seok Chung | 1 | 189 | 18.76 |
| Rajesh K. Gupta | 2 | 4570 | 390.84 |
| C. L. Liu | 3 | 6191 | 970.79 |