Name
Abstract | ||
|---|---|---|
This paper addresses delay test for SOC devices on low-cost testers. The case study focuses on the at-speed testing for a state-of-the-art micro-controller device by using an on-chip high-speed clock generator. The experimental results show that the simple on-chip highspeed clock generator is not sufficient to reach both high fault coverage and acceptable pattern count. Meanwhile, at-speed test constraints, required to enable the delay test on low cost testers, have a significant impact on test generation results. DFT techniques to increase fault coverage and to reduce pattern count are discussed. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/VTS.2005.54 | VTS |
Keywords | Field | DocType |
improve delay fault testing,high fault coverage,acceptable pattern count,at-speed testing,paper addresses delay test,delay test,at-speed test constraint,low-cost testers,pattern count,test generation result,case study,on-chip high-speed clock generator,fault coverage,system on chip,phase locked loops,production,microcontrollers,computer aided software engineering,chip,automatic test pattern generation | Stuck-at fault,Automatic test pattern generation,Clock generator,System on a chip,Fault coverage,Computer science,Real-time computing,Electronic engineering,Microcontroller | Conference |
ISSN | ISBN | Citations |
1093-0167 | 0-7695-2314-5 | 7 |
PageRank | References | Authors |
0.63 | 9 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Matthias Beck | 1 | 34 | 2.19 |
| Olivier Barondeau | 2 | 28 | 1.74 |
| Frank Poehl | 3 | 34 | 2.19 |
| Xijiang Lin | 4 | 687 | 42.03 |
| Ron Press | 5 | 113 | 9.12 |