Paper Info
Title
Benchmarking for research in power delivery networks of three-dimensional integrated circuits
Abstract
Power integrity is generally considered to be one of the major bottlenecks hindering the prevalence of three-dimensional integrated circuits (3D ICs). The higher integration density and smaller footprint result in significantly increased power density, which threatens the system reliability. In view of this, there has been groundswell of interest in academia to model, design or optimize the power delivery networks (PDNs) in 3D ICs. Unfortunately, while several PDN benchmarks exist for 2D PDNs, none is available in the context of 3D. As a consequence, most existing literature resorts to ad-hoc designs by artificially stacking 2D PDNs for experiments, rendering the results less convincing. In this paper, we put forward a set of ten PDN benchmarks that are extracted from industrial 3D designs. These designs are carefully selected such that they cover a wide range of functionality, size, TSV number, tier number and packaging style. We hope that the released benchmarks can facilitate and promote research in 3D PDNs.
Year
DOI
Venue
2013
10.1145/2451916.2451922
ISPD
Keywords
Field
DocType
power integrity,ad-hoc design,power density,existing literature resort,tsv number,higher integration density,power delivery network,three-dimensional integrated circuit,pdn benchmarks,major bottleneck,tier number,benchmark
Mathematical optimization,Computer science,Simulation,Power integrity,Power density,Footprint,Rendering (computer graphics),Integrated circuit,Reliability engineering,Benchmarking,Stacking
Conference
Citations 
PageRank 
References 
7
0.69
15
Authors
9
Name
Order
Citations
PageRank
Pei-Wen Luo1748.22
Chun Zhang2193.41
Yung-Tai Chang371.03
Liang-Chia Cheng4376.46
Hung-Hsie Lee570.69
Bih-Lan Sheu681.04
Yu-Shih Su71076.31
Ding-Ming Kwai852146.85
Yiyu Shi955383.22