Liang-Chia Cheng - Citegraph

Author Info

Name	Affiliation	Papers
LIANG-CHIA CHENG	Ind Technol Res Inst, Hsinchu, Taiwan	14
Collaborators	Citations	PageRank
60	37	6.46
Referers	Referees	References
98	382	129

Search Limit

100382

Publications (14 rows)

Collaborators (60 rows)

Referers (98 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Ping-Pong Mesh: A New Resonant Clock Design for Surge Current and Area Overhead Reduction.	0	0.34	2017
Thermal modeling and design on smartphones with heat pipe cooling technique.	1	0.43	2017
On the Optimal Threshold Voltage Computation of On-Chip Noise Sensors.	0	0.34	2016
Selective body biasing for post-silicon tuning of sub-threshold designs: A semi-infinite programming approach with Incremental Hypercubic Sampling.	0	0.34	2016
Incremental transient simulation of power grid	1	0.36	2014
Variation aware optimal threshold voltage computation for on-chip noise sensors	0	0.34	2014
Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells.	0	0.34	2014
A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS	2	0.42	2013
Benchmarking for research in power delivery networks of three-dimensional integrated circuits	7	0.69	2013
Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICs	0	0.34	2013
Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM	1	0.36	2013
Capturing the phantom of the power grid - on the runtime adaptive techniques for noise reduction	4	0.43	2012
Reliable Power Delivery System Design for Three-Dimensional Integrated Circuits (3D ICs)	1	0.35	2012
Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits	20	1.38	2008

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