Name
Title | ||
|---|---|---|
Logic synthesis for manufacturability considering regularity and lithography printability |
Abstract | ||
|---|---|---|
This paper presents a novel yield model for integrated circuits manufacturing, considering lithography printability problems as a source of yield loss. The use of regular layouts can improve the printability of IC layouts, but it results in a significant area overhead by introducing regularity. To the best of our knowledge, this is the first approach that considers the tradeoff of cells with different levels of regularity and different area overheads during the logic synthesis, in order to improve overall design yield. A technology remapping tool with such yield model as cost function is proposed and implemented and interesting results are presented. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ISVLSI.2013.6654638 | VLSI |
Keywords | Field | DocType |
design for manufacture,integrated circuit layout,lithography,IC layout,integrated circuit manufacturing,lithography printability,logic synthesis,technology remapping tool,yield loss,lithography,regularity,technology mapping,yield model | Integrated circuit layout,Logic synthesis,Semiconductor device modeling,Integrated circuit manufacturing,Electronic engineering,Lithography,Engineering,Integrated circuit,Design for manufacturability,Overhead (business) | Conference |
ISSN | Citations | PageRank |
2159-3469 | 0 | 0.34 |
References | Authors | |
0 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Lucas Machado | 1 | 0 | 1.01 |
| Vinícius Dal Bem | 2 | 19 | 4.07 |
| Francesc Moll | 3 | 55 | 14.87 |
| Sergio Gómez | 4 | 93 | 11.56 |
| Renato P. Ribas | 5 | 204 | 33.52 |
| André Inácio Reis | 6 | 134 | 21.33 |
| Dal Bem, V. | 7 | 0 | 0.34 |