Name
Abstract | ||
|---|---|---|
This paper shows an area-efficient and high-speed architecture for IPv6 lookup using a parallel index generation unit (IGU). To reduce the size of memory in the IGU, we use a liner transformation and a row-shift decomposition. Also, this paper shows a design method for the parallel IGU. A single memory realization requires O(2n) memory size, where n denotes the length of prefix, while the IGU requires O(nk) memory size, where k denotes the number of prefixes. In IPv6 prefix lookup, since n is at most 64 and k is about 340 K, the IGU drastically reduces the memory size. Since the parallel IGU has a simple architecture compared with existing ones, it performs lookup by using complete pipelines. We loaded more than 340 K IPv6 pseudo prefixes on the Xilinx Virtex 6 FPGA. Its lookup speed is higher than one giga lookups per second (GLPS). As for the normalized area and lookup speed, our implementation outperforms existing FPGA implementations. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1007/978-3-642-36812-7_6 | ARC |
Keywords | Field | DocType |
lookup speed,ipv6 lookup,high-speed architecture,single memory realization,memory size,k ipv6 pseudo prefix,parallel igu,parallel index generation unit,ipv6 prefix lookup,fpga implementation | IPv6,Normalization (statistics),Giga-,Computer science,Parallel computing,Field-programmable gate array,Real-time computing,Prefix,IPv6 address,Border Gateway Protocol,Virtex | Conference |
Volume | ISSN | Citations |
7806 | 0302-9743 | 3 |
PageRank | References | Authors |
0.50 | 10 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hiroki Nakahara | 1 | 155 | 37.34 |
| Tsutomu Sasao | 2 | 1083 | 141.62 |
| Munehiro Matsuura | 3 | 189 | 24.44 |