Hiroki Nakahara - Citegraph

Author Info

Name	Affiliation	Papers
HIROKI NAKAHARA	The authors are with the Department of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka-shi, 820-8502 Japan. E-mail: nakahara@aries01.cse.kyutech.ac.jp, E-mail: sasao@cse.k ...	90
Collaborators	Citations	PageRank
80	155	37.34
Referers	Referees	References
354	637	457

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Publications (90 rows)

Collaborators (80 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner	1	0.37	2021
A High-Throughput Detection Circuit based on 2 q +1-Valued Deep Neural Networks	0	0.34	2021
A Novel Compact Planar Magic-T Using Cps And Microstrip-To-Cps Transition	0	0.34	2021
Energy-Efficient Ecg Signals Outlier Detection Hardware Using A Sparse Robust Deep Autoencoder	0	0.34	2021
A Low-Latency Inference of Randomly Wired Convolutional Neural Networks on an FPGA	0	0.34	2021
A Multilayer Perceptron Training Accelerator using Systolic Array	0	0.34	2021
Weight Sparseness for a Feature-Map-Split-CNN Toward Low-Cost Embedded FPGAs	0	0.34	2021
Fpga-Based Inter-Layer Pipelined Accelerators For Filter-Wise Weight-Balanced Sparse Fully Convolutional Networks With Overlapped Tiling	1	0.43	2021
A Table Look-Up Based Ternary Neural Network Processor	1	0.38	2020
An FPGA-Based Low-Latency Accelerator for Randomly Wired Neural Networks	0	0.34	2020
2<sup>n</sup>+1-valued SSS-Net: Uniform Shift, Channel Sparseness, and Channel Shuffle	0	0.34	2020
Optimizing Reconfigurable Recurrent Neural Networks	1	0.39	2020
R2CNN - Recurrent Residual Convolutional Neural Network on FPGA.	0	0.34	2020
Tiny On-Chip Memory Realization of Weight Sparseness Split-CNNs on Low-end FPGAs	0	0.34	2020
A Reconfigurable Multithreaded Accelerator for Recurrent Neural Networks	0	0.34	2020
Design Method for an LUT Network-Based CNN with a Sparse Local Convolution	0	0.34	2020
Fast Monocular Depth Estimation on an FPGA	0	0.34	2020
High-Throughput Convolutional Neural Network on an FPGA by Customized JPEG Compression	1	0.40	2020
Sentei: Filter-Wise Pruning With Distillation Towards Efficient Sparse Convolutional Neural Network Accelerators	0	0.34	2020
Guinness: A Gui Based Binarized Deep Neural Network Framework For Software Programmers	0	0.34	2019
An FPGA-based Fine Tuning Accelerator for a Sparse CNN.	1	0.35	2019
Filter-Wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation.	2	0.53	2019
Power Efficient Object Detector With An Event-Driven Camera For Moving Object Surveillance On An Fpga	0	0.34	2019
Real-Time Multi-Pedestrian Detection in Surveillance Camera using FPGA	0	0.34	2019
FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network	1	0.36	2019
A Dataflow Pipelining Architecture for Tile Segmentation with a Sparse MobileNet on an FPGA	0	0.34	2019
An FPGA Implementation of Real-Time Object Detection with a Thermal Camera	0	0.34	2019
Noise Convolutional Neural Networks and FPGA Implementation	0	0.34	2019
FPGA-based Accurate Pedestrian Detection with Thermal Camera for Surveillance System	0	0.34	2019
Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks	0	0.34	2019
An FPGA Realization of OpenPose Based on a Sparse Weight Convolutional Neural Network	1	0.37	2018
A Ternary Weight Binary Input Convolutional Neural Network: Realization on the Embedded Processor	1	0.38	2018
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W.	15	0.85	2018
A Performance Per Power Efficient Object Detector On An Fpga For Robot Operating System (Ros)	0	0.34	2018
A Tri-State Weight Convolutional Neural Network for an FPGA: Applied to YOLOv2 Object Detector	0	0.34	2018
A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA.	2	0.49	2018
An Fpga Realization Of A Random Forest With K-Means Clustering Using A High-Level Synthesis Design	0	0.34	2018
A Demonstration of FPGA-Based You Only Look Once Version2 (YOLOv2)	0	0.34	2018
Power Efficient Object Detector With An Event-Driven Camera On An Fpga	0	0.34	2018
A Threshold Neuron Pruning For A Binarized Deep Neural Network On An Fpga	1	0.35	2018
New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications	0	0.34	2018
Demonstration of Object Detection for Event-Driven Cameras on FPGAs and GPUs	0	0.34	2018
An FPGA Realization of a Deep Convolutional Neural Network Using a Threshold Neuron Pruning.	1	0.35	2017
All binarized convolutional neural network and its implementation on an FPGA	3	0.72	2017
A Random Forest Using a Multi-valued Decision Diagram on an FPGA	2	0.39	2017
In-memory area-efficient signal streaming processor design for binary neural networks	1	0.38	2017
On-Chip Memory Based Binarized Convolutional Deep Neural Network Applying Batch Normalization Free Technique on an FPGA	7	0.74	2017
A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only).	4	0.43	2017
An object detector based on multiscale sliding window search using a fully pipelined binarized CNN on an FPGA	0	0.34	2017
An FFT Circuit Using Nested RNS in a Digital Spectrometer for a Radio Telescope	0	0.34	2016

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