Name
Title | ||
|---|---|---|
A general design methodology for synchronous early-completion-prediction adders in nano-CMOS DSP architectures |
Abstract | ||
|---|---|---|
Synchronous early-completion-prediction adders (ECPAs) are used for high clock rate and high-precision DSP datapaths, as they allow a dominant amount of single-cycle operations even if the worst-case carry propagation delay is longer than the clock period. Previous works have also demonstrated ECPA advantages for average leakage reduction and NBTI effects reduction in nanoscale CMOS technologies. This paper illustrates a general systematic methodology to design ECPA units, targeting nanoscale CMOS technologies, which is not available in the current literature yet. The method is fully compatible with standard VLSI macrocell design tools and standard adder structures and includes automatic definition of critical test patterns for postlayout verification. A design example is included, reporting speed and power data superior to previous works. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1155/2013/785281 | VLSI Design |
Keywords | Field | DocType |
general design methodology,ecpa unit,nbti effects reduction,average leakage reduction,design example,previous work,ecpa advantage,nano-cmos dsp architecture,nanoscale cmos technology,synchronous early-completion-prediction adder,standard vlsi macrocell design,high clock rate,clock period | Digital signal processing,Leakage (electronics),Adder,Computer science,Design methods,Real-time computing,Electronic engineering,Very-large-scale integration,Automatic transmission,Macrocell,Clock rate,Embedded system | Journal |
Volume | ISSN | Citations |
2013, | 1065-514X | 1 |
PageRank | References | Authors |
0.35 | 9 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mauro Olivieri | 1 | 385 | 36.09 |
| Antonio Mastrandrea | 2 | 23 | 6.24 |