Paper Info
Title
Networks on Chips: from research to products
Abstract
Research on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address the chip-level interconnect problem has been shown to be correct. Moreover, as technology scales down in geometry and chips scale up in complexity, NoCs become the essential element to achieve the desired levels of performance and quality of service while curbing power consumption levels. Design and timing closure can only be achieved by a sophisticated set of tools that address NoC synthesis, optimization and validation.
Year
DOI
Venue
2010
10.1145/1837274.1837352
Design Automation Conference
Keywords
Field
DocType
noc synthesis,networking technology,sophisticated set,essential element,technology scale,timing closure,power consumption level,seminal idea,field programmable gate arrays,noc,chip,network on a chip,quality of service,topology,soc,computer architecture,integrated circuit design,network on chip,system on a chip,system performance,system on chip
System on a chip,Computer science,Network on a chip,Quality of service,Electronic engineering,Real-time computing,Integrated circuit design,Interconnection,Timing closure,Power consumption,Embedded system
Conference
ISSN
ISBN
Citations 
0738-100X
978-1-4244-6677-1
23
PageRank 
References 
Authors
0.89
30
6
Name
Order
Citations
PageRank
Giovanni De Micheli1102451018.13
Ciprian Seiculescu22199.26
S. Murali3291.71
Luca Benini4131161188.49
F. Angiolini51448.26
Antonio Pullini639028.27