Name
Abstract | ||
|---|---|---|
Modern out-of-order processors tolerate long-latency memory operations by supporting a large number of in-flight instructions. This is achieved in part through proper sizing of critical resources, such as register files or instruction queues. In light of the increasing gap between processor speed and memory latency, tolerating upcoming latencies in this way would require impractical sizes of such critical resources.To tackle this scalability problem, we make a case for resource-conscious out-of-order processors. We present quantitative evidence that critical resources are increasingly underutilized in these processors. We advocate that better use of such resources should be a priority in future research in processor architectures. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/L-CA.2003.4 | Computer Architecture Letters |
Keywords | Field | DocType |
memory latency,modern out-of-order processor,processor architecture,processor speed,resource-conscious out-of-order processor,better use,index terms—out-of-order processor,instruction-level parallelism,resource utilization.,long-latency memory operation,critical resource,impractical size,out of order,indexing terms,instruction level parallelism,register file,resource utilization | Instruction-level parallelism,Instruction register,Computer science,Very long instruction word,Parallel computing,Real-time computing,Processor register,Out-of-order execution,CAS latency,Clock rate,Scalability | Journal |
Volume | Issue | ISSN |
2 | 1 | 1556-6056 |
Citations | PageRank | References |
10 | 0.70 | 11 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Adrian Cristal | 1 | 500 | 32.64 |
| José-jesús Fernández | 2 | 1584 | 111.72 |
| Josep Llosa | 3 | 574 | 39.30 |
| Mateo Valero | 4 | 4520 | 355.94 |