Paper Info
Title
Design of cross-point metal-oxide ReRAM emphasizing reliability and cost
Abstract
Metal-Oxide Resistive Random Access Memory (ReRAM) technology is gaining popularity due to its superior write bandwidth, high density, and low operating power. An ReRAM array structure can be built with three different approaches: a traditional design with a dedicated access transistor (1T1R) or an access diode (1D1R) for each cell, or an intrinsic cross-point structure (0T1R), where the metal-oxide is directly sandwiched between the horizontal and vertical wires. Each of these different structures has its advantages and disadvantages, and it is a complicated process to perform a systematic comparison of delay, energy, area, and cost of one over others for a given cell parameters set and technology. In this paper, we analyze both advantages and disadvantages for ReRAM arrays built in 1T1R, 1D1R, and 0T1R structures. Based on the analysis, we propose a design flow and provides key insights into architectural tradeoffs. We do this in three stages: first, we use a matrix-based mathematical model to determine the optimal array size, read/write bandwidth, and other key characteristics. This acts as input to the second stage to explore the design space of ReRAM banks and the entire chip. Finally, we estimate the chip-level cost using the area, metal layers, pin count, and cooling requirements. Using the proposed model, we also present a case study in which we compare the energy, performance, and area of a 1D1R cross-point design and a 0T1R design, and show that the 1D1R structure is more promising for a cost-driven memory design.
Year
DOI
Venue
2013
10.1109/ICCAD.2013.6691092
ICCAD
Keywords
Field
DocType
design space,design flow,traditional design,intrinsic cross-point structure,reram array structure,cost-driven memory design,reram bank,access diode,cross-point design,different structure,integrated circuit design
Array data structure,Computer science,Diode,Design flow,Chip,Electronic engineering,Bandwidth (signal processing),Integrated circuit design,Transistor,Electrical engineering,Resistive random-access memory
Conference
ISSN
ISBN
Citations 
1933-7760
978-1-4799-1069-4
14
PageRank 
References 
Authors
1.75
8
5
Name
Order
Citations
PageRank
Dimin Niu160931.36
Cong Xu2115448.25
Naveen Muralimanohar3129557.58
Norman P. Jouppi46042791.53
Yuan Xie56430407.00