Name
Abstract | ||
|---|---|---|
This paper describes an efficient graph-based method to optimize data-flow expressions for best hardware implementation. The method is based on factorization, common subexpression elimination (CSE) and decomposition of algebraic expressions performed on a canonical representation, Taylor Expansion Diagram. The method is generic, applicable to arbitrary algebraic expressions and does not require specific knowledge of the application domain. Experimental results show that the DFGs generated from such optimized expressions are better suited for high level synthesis, and the final, scheduled implementations are characterized, on average, by 15.5% lower latency and 7.6% better area than those obtained using traditional CSE and algebraic decomposition. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/DATE.2009.5090643 | DATE |
Keywords | Field | DocType |
optimizing data flow graph,application domain,canonical representation,arbitrary algebraic expression,taylor expansion,traditional cse,better area,efficient graph-based method,algebraic decomposition,algebraic expression,best hardware implementation,data flow,digital circuits,additives,polynomials,systematics,digital signal processing,design optimization,hardware,arithmetic,common subexpression elimination,high level synthesis,optimization,topology,placement,data flow graph | Common subexpression elimination,Algebraic number,Expression (mathematics),Polynomial,Computer science,High-level synthesis,Parallel computing,Algorithm,Canonical form,Algebraic expression,Computer hardware,Data flow diagram | Conference |
ISSN | Citations | PageRank |
1530-1591 | 8 | 0.60 |
References | Authors | |
9 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| D. Gomez-Prado | 1 | 27 | 2.39 |
| Q. Ren | 2 | 8 | 0.60 |
| Maciej J. Ciesielski | 3 | 629 | 74.80 |
| J. Guillot | 4 | 8 | 0.60 |
| E. Boutillon | 5 | 20 | 3.37 |