Name
Abstract | ||
|---|---|---|
Wavelet transform coding has been drawing much attention because of its ability to decompose images into a hierarchical structure that is suitable for adaptive processing in the transform domain. This paper presents an Efficient VLSI design of one-dimensional direct discrete wavelet transform processor. The proposed architecture computes three DWT stages and uses four parallel filters. The architecture is simple and offers 16-bit precision on input and output data. It is constituted of three basic units: one storage unit, four filters, and a control unit. No memory or registers are used for storing intermediate results. Furthermore, data scheduling and memory management remain very simple. The end result is an efficient VLSI implementation with a reduced area cost compared to the conventional approaches. The architecture can compute DWT at a data rate of 7 x 10(6) samples/s corresponding to a typical clock speed of 7 MHz. The architecture is simulated and verified at the gate level in VLSI. Process parameters used were those of 0.6 mum technology. The chip area is about 15.7 mm(2). (C) 2000 Elsevier Science B.V. All rights reserved. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1016/S0167-9260(00)00007-9 | Integration |
Keywords | Field | DocType |
parallel filter,1-d dwt architecture,vlsi design,memory management,chip,discrete wavelet transform,wavelet transform | Computer science,Electronic engineering,Input/output,Memory management,Adaptive filter,Control unit,Discrete wavelet transform,Very-large-scale integration,Clock rate,Wavelet transform | Journal |
Volume | Issue | ISSN |
29 | 2 | Integration, the VLSI Journal |
Citations | PageRank | References |
10 | 0.81 | 17 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chokri Souani | 1 | 41 | 8.75 |
| Mohamed Abid | 2 | 24 | 3.76 |
| Kholdoun Torki | 3 | 60 | 6.70 |
| Rached Tourki | 4 | 144 | 25.21 |