Paper Info
Title
A 1r/1w Sram Cell Design To Keep Cell Current And Area Saving Against Simultaneous Read/Write Disturbed Accesses
Abstract
A guarantee obligation of keeping a Static-Noise-Margin (SNM), a Write-Margin (WRTM), and a cell current (Icell) even against a simultaneous Read/Write (R/W) disturbed access at the same column is required for a 1R/1W (1R/1W) SRAM. We have verified that it is difficult for the previously proposed techniques [1]-[5] so far to meet all the requirements simultaneously without any decrease in Icell or any significant area penalty. In order to address this issue, a new cell design technique for the 1R/1W SRAM cell with 8Tr's has been proposed and demonstrated in a 65 ran CMOS technology. It has been shown that Icell in the R/W disturbed column can be increased by 77% and 195% at V-dd=0.9 V and 0.6 V, respectively, and a cell size can be reduced by 15%, compared with the conventional column-based cell power-terminal bias (VDDM) control [1], [2] assuming that the same Icell of 9 mu A at V-dd=0.9 V has to be provided. Compared with the conventional scheme, it has been found that the proposed Write-Bit-Line precharge level (VWBL) control and column-based cell source-terminal bias (VSSM) control can provide a 1.45-times larger SNM for Write-Word-Line (WWL) disturbed cells and a 1.7-fold larger WRTM while keeping the same Icell, respectively.
Year
DOI
Venue
2007
10.1093/ietele/e90-c.4.749
IEICE TRANSACTIONS ON ELECTRONICS
Keywords
Field
DocType
SRAM, 1R/1W-SRAM, disturbed access, SNM, write margin, cell current
Static random-access memory,Electronic engineering,CMOS,Sram cell,Miniaturization,Engineering,Electrical engineering,Cell design,Integrated circuit,Write margin
Journal
Volume
Issue
ISSN
E90C
4
1745-1353
Citations 
PageRank 
References 
5
1.60
0
Authors
3
Name
Order
Citations
PageRank
Hiroyuki Yamauchi118030.79
Toshi-kazu Suzuki27311.00
Yoshinobu Yamagami36710.80