A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses | 33 | 1.95 | 2008 |
A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations. | 29 | 6.58 | 2007 |
A 1r/1w Sram Cell Design To Keep Cell Current And Area Saving Against Simultaneous Read/Write Disturbed Accesses | 5 | 1.60 | 2007 |
A Differential Cell Terminal Biasing Scheme Enabling A Stable Write Operation Against A Large Random Threshold Voltage (V-Th) Variation | 0 | 0.34 | 2006 |
0.3-1.5v Embedded Sram Core With Write-Replica Circuit Using Asymmetrical Memory Cell And Source-Level-Adjusted Direct-Sense-Amplifier | 0 | 0.34 | 2005 |