Name
Abstract | ||
|---|---|---|
A design method of totally self-checking (TSC) m-out-of-2m code checkers is presented. The design is composed basically of two full-adder/half-adder trees, each summing up the ones received on m input lines, and a k-variable two-pair two-rail code tree that compares the outputs of the two-adder tree. The only modules used are full-adders, half-adders, and two-variable TSC two-rail code checkers. This method is well suited for VLSI MOS implementation and, compared to previous methods, it results in significant circuit cost reduction and smaller test set, without sacrificing performance. Also, the proposed design has the advantages of a modular design. |
Year | DOI | Venue |
|---|---|---|
1988 | 10.1109/12.2167 | IEEE Trans. Computers |
Keywords | Field | DocType |
vlsi mos implementation,m-out-of-2m code checker,efficient modular design,half-adder tree,two-variable tsc two-rail code,tsc checkers,two-adder tree,previous method,modular design,k-variable two-pair two-rail code,design method,proposed design,fault detection,half adder,full adder,logic design,codes,very large scale integration,adders,design methodology | Logic synthesis,Adder,Computer science,Parallel computing,Error detection and correction,Fault tolerance,Modular design,Integrated circuit,Very-large-scale integration,Test set | Journal |
Volume | Issue | ISSN |
37 | 3 | 0018-9340 |
Citations | PageRank | References |
17 | 2.34 | 7 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| A. Paschalis | 1 | 358 | 31.08 |
| D. Nikolos | 2 | 291 | 31.38 |
| C. Halatsis | 3 | 18 | 3.07 |