Paper Info
Title
Enhancing 3T DRAMs for SRAM replacement under 10nm tri-gate SOI FinFETs
Abstract
In this paper, we present the dynamic 3T memory cell for future 10nm tri-gate FinFETs as a potential replacement for classical 6T SRAM cell for implementation in high speed cache memories. We investigate read access time, retention time, and static power consumption of the cell when it is exposed to the effects of process and environmental variations. Process variations are extracted from the ITRS predictions and they are modeled at device level. For simulation, we use 10nm SOI tri-gate FinFET BSIM-CMG model card developed by the University of Glasgow, Device Modeling Group. When compared to the classical 6T SRAM, 3T cell has 40% smaller area, leakage is reduced up to 14 times while access time is approximately the same. In order to achieve higher retention times, we propose several cell extensions which, at the same time, enable post-fabrication/run-time adaptability.
Year
DOI
Venue
2012
10.1109/ICCD.2012.6378657
ICCD
Keywords
DocType
Citations 
higher retention time,access time,process variation,sram cell,tri-gate soi finfets,tri-gate finfets,sram replacement,device modeling group,soi tri-gate finfet bsim-cmg,memory cell,retention time,cell extension,logic gates,computer architecture
Conference
0
PageRank 
References 
Authors
0.34
0
1
Name
Order
Citations
PageRank
Ramon Canal175650.02