| Transfer-Learning-Based Intrusion Detection Framework in IoT Networks | 0 | 0.34 | 2022 |
| A Real-Time Error Detection (RTD) Architecture and Its Use for Reliability and Post-Silicon Validation for F/F Based Memory Arrays | 0 | 0.34 | 2022 |
| SafeX: Open Source Hardware and Software Components for Safety-Critical Systems | 0 | 0.34 | 2022 |
| A Survey of Deep Learning Techniques for Cybersecurity in Mobile Networks | 0 | 0.34 | 2021 |
| 2D Error Correction for F/F based Arrays using In-Situ Real-Time Error Detection (RTD) | 0 | 0.34 | 2020 |
| Cross-Layer Soft-Error Resilience Analysis of Computing Systems | 0 | 0.34 | 2020 |
| Protecting RSA Hardware Accelerators against Differential Fault Analysis through Residue Checking | 0 | 0.34 | 2019 |
| Challenges in Deeply Heterogeneous High Performance Systems | 0 | 0.34 | 2019 |
| Modem Gain-Cell Memories in Advanced Technologies | 0 | 0.34 | 2018 |
| Optimization of FinFET-Based Gain Cells for Low Power Sub-V T Embedded DRAMs. | 0 | 0.34 | 2018 |
| MeRLiN: Exploiting Dynamic Instruction Behavior for Fast and Accurate Microarchitecture Level Reliability Assessment. | 2 | 0.36 | 2017 |
| Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level | 0 | 0.34 | 2017 |
| Feasibility of Embedded DRAM Cells on FinFET Technology. | 1 | 0.36 | 2016 |
| Statistical analysis and comparison of 2T and 3T1D e-DRAM minimum energy operation. | 1 | 0.36 | 2016 |
| MASkIt: Soft error rate estimation for combinational circuits | 1 | 0.36 | 2016 |
| SRAM memory margin probability failure estimation using Gaussian Process regression | 0 | 0.34 | 2016 |
| A detailed methodology to compute Soft Error Rates in advanced technologies. | 2 | 0.36 | 2016 |
| Variability Influence On Finfet-Based On-Chip Memory Data Paths | 0 | 0.34 | 2015 |
| Cross-layer early reliability evaluation: Challenges and promises | 2 | 0.37 | 2014 |
| DRAM-based coherent caches and how to take advantage of the coherence protocol to reduce the refresh energy | 1 | 0.35 | 2014 |
| REEM: Failure/non-failure region estimation method for SRAM yield analysis | 0 | 0.34 | 2014 |
| SSFB: a highly-efficient and scalable simulation reduction technique for SRAM yield analysis | 2 | 0.40 | 2014 |
| Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm. | 0 | 0.34 | 2014 |
| Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes | 5 | 0.43 | 2013 |
| An energy-efficient and scalable eDRAM-based register file architecture for GPGPU | 42 | 1.12 | 2013 |
| Effectiveness Of Hybrid Recovery Techniques On Parametric Failures | 2 | 0.40 | 2013 |
| Enhancing Performance and Energy Consumption of HER Caches by Adding Associativity. | 0 | 0.34 | 2013 |
| Thread Row Buffers: Improving Memory Performance Isolation and Throughput in Multiprogrammed Environments | 6 | 0.45 | 2013 |
| Distributed Cooperative Caching: An Energy Efficient Memory Scheme for Chip Multiprocessors | 6 | 0.51 | 2012 |
| A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance | 1 | 0.37 | 2012 |
| Enhancing 3T DRAMs for SRAM replacement under 10nm tri-gate SOI FinFETs | 0 | 0.34 | 2012 |
| Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors | 1 | 0.37 | 2011 |
| TRAMS Project: Variability and Reliability of SRAM Memories in sub-22 nm Bulk-CMOS Technologies. | 0 | 0.34 | 2011 |
| Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells | 1 | 0.39 | 2011 |
| Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors | 28 | 0.91 | 2010 |
| Power-efficient spilling techniques for chip multiprocessors | 2 | 0.37 | 2010 |
| MODEST: a model for energy estimation under spatio-temporal variability | 2 | 0.64 | 2010 |
| Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs | 5 | 0.43 | 2009 |
| An hybrid eDRAM/SRAM macrocell to implement first-level data caches | 18 | 1.05 | 2009 |
| Power/Performance/Thermal Design-Space Exploration for Multicore Architectures | 41 | 1.59 | 2008 |
| Distributed cooperative caching | 21 | 0.83 | 2008 |
| Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability | 17 | 1.17 | 2008 |
| Process Variation Tolerant 3T1D-Based Cache Architectures | 219 | 9.65 | 2007 |
| Design space exploration for multicore architectures: a power/performance/thermal view | 58 | 1.85 | 2006 |
| Value compression for efficient computation | 1 | 0.35 | 2005 |
| Power- and Complexity-Aware Issue Queue Designs | 13 | 0.67 | 2003 |
| Dynamic code partitioning for clustered architectures | 10 | 0.85 | 2001 |
| Reducing the complexity of the issue logic | 40 | 1.55 | 2001 |
| Dynamic Cluster Assignment Mechanisms | 73 | 4.11 | 2000 |
| Very low power pipelines using significance compression | 59 | 3.59 | 2000 |
