Name
Abstract | ||
|---|---|---|
In this paper, we present a new BIST test pattern generator architecture and a methodology to program this architecture to generate tests for any given inter-chip interconnect circuitry via IEEE 1149.1 boundary-scan architecture. The test architecture uses two test pattern generators, a C-TPG that generates test patterns for the control cells in the boundary scan chain and a D-TPG that generates test patterns for the data cells. The other main component of the test architecture is a lookup table which is programmed to select, for each boundary scan cell, a specific C-TPG or D-TPG stage whose content is shifted into that cell. This test architecture provides a complete BIST solution for interconnect testing. The proposed BIST TPG design procedure uses the notions of incompatibility and conditional incompatibility and generates TPG designs that (i) guarantee that no circuit damage can occur due to multi-driver conflicts, (ii) guarantee the detection of all interconnect faults, (iii) have low area overhead, and (iv) have low test length. The proposed procedure is used to obtain TPG designs that require significantly less test time and area than other TPG designs, for eight interconnect circuits extracted from industrial boards. |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1109/VTEST.1997.600311 | VTS |
Keywords | Field | DocType |
boundary scan,new bist test pattern,generator architecture,tpg design,boundary-scan architecture,test architecture,test pattern,board level interconnect,low test length,test time,proposed bist tpg design,bist tpgs,test pattern generator,chip,lookup table | Boundary scan,Automatic test pattern generation,Lookup table,Architecture,Computer science,Electronic engineering,Electronic circuit,Interconnection,Test compression,Built-in self-test,Embedded system | Conference |
ISSN | ISBN | Citations |
1093-0167 | 0-8186-7810-0 | 18 |
PageRank | References | Authors |
1.14 | 12 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chen-Huan Chiang | 1 | 53 | 7.33 |
| Sandeep K. Gupta Electrical Engineering -- Systems | 2 | 18 | 1.14 |