Name
Abstract | ||
|---|---|---|
The combination of flit-buffer flow control methods and latency-insensitive protocols is an effective solution for networks-on-chip (NoC). Since they both rely on backpressure, the two techniques are easy to combine while offering complementary advantages: low complexity of router design and the ability to cope with long communication channels via automatic wire pipelining. We study various alternative implementations of this idea by considering the combination of three different types of flit-buffer flow control methods and two different classes of channel repeaters (based respectively on flip-flops and relay stations). We characterize the area and performance of the two most promising alternative implementations for NoCs by completing the RTL design and logic synthesis of the repeaters and routers for different channel parallelisms. Finally, we derive high-level abstractions of our circuit designs and we use them to perform system-level simulations under various scenarios for two distinct NoC topologies and various applications. Based on our comparative analysis and experimental results, we propose a NoC design approach that combines the reduction of the router queues to a minimum size with the distribution of flit buffering onto the channels. This approach provides precious flexibility during the physical design phase for many NoCs, particularly in those systems-on-chip that must be designed to meet a tight constraint on the target clock frequency. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1145/1450135.1450183 | CODES+ISSS |
Keywords | Field | DocType |
noc design approach,circuit design,distinct noc topology,rtl design,router design,different class,physical design phase,different channel parallelism,different type,flit-buffer flow control method,flow control,logic synthesis,chip,physical design,network on chip,communication channels,system on chip | Computer science,Network on a chip,Communication channel,Network topology,Real-time computing,Router,Physical design,Repeater,Clock rate,Relay | Conference |
Citations | PageRank | References |
10 | 0.78 | 17 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Nicola Concer | 1 | 164 | 8.90 |
| Michele Petracca | 2 | 239 | 16.21 |
| Luca P. Carloni | 3 | 1713 | 120.17 |