Name
Abstract | ||
|---|---|---|
For multigigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register (RDR) microarchitecture, which offers high regularity and direct support of multicycle on-chip communication. The RDR microarchitecture divides the entire chip into an array of islands so that all local computation and communication within an island can be performed in a single clock cycle. Each island contains a cluster of computational elements, local registers, and a local controller. On top of the RDR microarchitecture, novel layout-driven architectural synthesis algorithms have been developed for multicycle communication, including scheduling-driven placement, placement-driven simultaneous scheduling with rebinding, and distributed control generation, etc. The experimentation on a number of real-life examples demonstrates promising results. For data flow intensive examples, we obtain a 44% improvement on average in terms of the clock period and a 37% improvement on average in terms of the final latency, over the traditional flow. For designs with control flow, our approach achieves a 28% clock-period reduction and a 23% latency reduction on average. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/TCAD.2004.825872 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
multicycle on-chip communication,control flow,local computation,on-chip multicycle communication,RDR microarchitecture,multiple clock cycle,multicycle communication,local register,clock period,single clock cycle,local controller | Journal | 23 |
Issue | ISSN | Citations |
4 | 0278-0070 | 42 |
PageRank | References | Authors |
1.71 | 25 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jason Cong | 1 | 7069 | 515.06 |
| Yiping Fan | 2 | 456 | 25.67 |
| Guoling Han | 3 | 313 | 17.17 |
| Xun Yang | 4 | 42 | 1.71 |
| Zhiru Zhang | 5 | 1020 | 71.74 |