Paper Info
Title
Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture
Abstract
With the advent of Networks-on-Chip (NoCs), the interest for mesochronous synchronizers is again on the rise due to the intricacies of skew-controlled chip-wide clock tree distribution. Recently proposed schemes agree on a source synchronous design style with some form of ping-pong buffering to counter timing and metastability concerns. However, the integration issues of such synchronizers in a NoC setting are still largely uncovered. Most schemes are in fact placed between communicating switches, thus neglecting the abrupt increase of buffering resources needed at switch input stages. This paper goes a step forward and aims at deep integration of the synchronizer in the switch architecture, thus merging key tasks such as synchronization, buffering and flow control into a unique architecture block. This paper compares the integrated and the loosely coupled solutions from a performance and area viewpoint, while devoting special attention to their robustness with respect to physical design parameters.
Year
DOI
Venue
2009
10.1109/NOCS.2009.5071473
NOCS
Keywords
Field
DocType
mesochronous synchronizers,noc setting,switch architecture,buffering resource,source synchronous design style,deep integration,unique architecture block,physical design parameter,integration issue,noc switch architecture,switch input stage,phase detection,chip,metastability,computer architecture,detectors,radiation detectors,flow control,network on a chip,switches,synchronization,synchronisation,network on chip,physical design
Architecture,Synchronization,Synchronizer,Computer science,Network on a chip,Real-time computing,Robustness (computer science),Flow control (data),Physical design,Source-synchronous
Conference
Citations 
PageRank 
References 
11
0.61
16
Authors
5
Name
Order
Citations
PageRank
Daniele Ludovici1614.92
Alessandro Strano2646.67
Davide Bertozzi3165399.83
Luca Benini4131161188.49
Georgi Gaydadjiev51117104.92