Alessandro Strano - Citegraph

Author Info

Name	Affiliation	Papers
ALESSANDRO STRANO	ENDIF, University of Ferrara, Ferrara, Italy	15
Collaborators	Citations	PageRank
29	64	6.67
Referers	Referees	References
172	528	249

Search Limit

100528

Publications (15 rows)

Collaborators (29 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A feature-rich NoC switch with cross-feature optimizations for the next generation of reliable and reconfigurable embedded systems	2	0.38	2014
Optimising pseudo-random built-in self-testing of fully synchronous as well as multisynchronous networks-on-chip.	0	0.34	2013
Enabling power efficiency through dynamic rerouting on-chip	0	0.34	2013
An efficient, low-cost routing framework for convex mesh partitions to support virtualization	0	0.34	2013
A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs	8	0.56	2013
Cooperative Built-in Self-Testing and Self-Diagnosis of NoC Bisynchronous Channels	4	0.41	2012
Evaluation of GALS Methods in Scaled CMOS Technology: Moonrake Chip Experience.	0	0.34	2012
Optimizing built-in pseudo-random self-testing for network-on-chip switches	1	0.38	2012
Power efficiency of switch architecture extensions for fault tolerant NoC design	4	0.47	2012
OSR-Lite: Fast and deadlock-free NoC reconfiguration framework	12	0.65	2012
Mesochronous NoC technology for power-efficient GALS MPSoCs	3	0.39	2011
Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design	0	0.34	2011
A library of dual-clock FIFOs for cost-effective and flexible MPSoC design	12	0.60	2010
Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture	11	0.61	2009
Architecture design principles for the integration of synchronization interfaces into Network-on-Chip switches	7	0.54	2009

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