Name
Abstract | ||
|---|---|---|
Testing a secure system is often considered as a severebottleneck. While testability requires to an increase inboth observability and controllability, secure chips aredesigned with the reverse in mind, limiting access to chipcontent and on-chip controllability functions. As a result,using usual design for testability techniques whendesigning secure ICs may seriously decrease the level ofsecurity provided by the chip. This dilemma is even moresevere as secure applications need well-tested hardwareto ensure that the programmed operations are correctlyexecuted. In this paper, a security analysis of the scantechnique is performed. This analysis aims at pointing outthe security vulnerability induced by using such a DfTtechnique. A solution securing the scan is finally proposed. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/IOLTS.2004.40 | IOLTS |
Keywords | Field | DocType |
increase inboth observability,outthe security vulnerability,secure ics,secure chip,on-chip controllability function,secure system,security analysis,secure application,scan design,testability technique,level ofsecurity,chip,design for testability | Testability,Design for testing,Observability,Vulnerability (computing),Controllability,Computer science,Real-time computing,Chip,Security analysis,Limiting | Conference |
ISBN | Citations | PageRank |
0-7695-2180-0 | 49 | 4.63 |
References | Authors | |
7 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| david hely | 1 | 102 | 10.43 |
| Marie-Lise Flottes | 2 | 366 | 45.31 |
| Frederic Bancel | 3 | 105 | 10.22 |
| Bruno Rouzeyre | 4 | 456 | 49.44 |
| Nicolas Berard | 5 | 49 | 4.63 |
| Michel Renovell | 6 | 749 | 96.46 |