Name
Abstract | ||
|---|---|---|
Pre-bond testing of 3D stacked ICs involves testing individual dies before bonding. The overall yield of 3D ICs improves with pre-bond testability because designers can avoid stacking defective dies with good ones. However, pre-bond testability presents unique challenges to 3D clock tree design. First, each die needs a complete 2D clock tree for the pre-bond testing. In addition, the entire 3D stack needs a complete 3D clock tree for post-bond testing and normal operations. In the case of two-die stack, a straightforward solution is to have two complete 2D clock trees connected with a single Through-Silicon-Via (TSV). We show that this solution suffers from long wirelength and high clock power consumption. Instead, our algorithm minimizes the overall wirelength and clock power consumption while providing the pre-bond testability and post-bond operability under given skew and slew constraints. Compared with the single-TSV solution, SPICE simulation results show that our multi-TSV approach significantly reduces the clock power by up to 15.9% for two-die and 29.7% for four-die stack. In addition, the wirelength reduction is up to 24.4% and 42.0%. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1145/1687399.1687433 | ICCAD |
Keywords | Field | DocType |
microassembling,spice simulation,spice,integrated circuit testing,integrated circuit interconnections,clock tree,integrated circuit metallisation,pre-bond testable low-power clock,3d stacked ic,three-dimensional integrated circuits,clock tree design,timing,pre-bond testability,testable low power clock tree design,overall wirelength,die testing,high clock power consumption,clock power,stacking defective die,clock power consumption,post-bond testing,multi through silicon via,synchronisation,pre-bond testing,long wirelength,capacitance,performance,testing,merging,timing analysis,normal operator,through silicon via,logic synthesis,throughput | Logic synthesis,Testability,Clock gating,Synchronization,Spice,Computer science,Electronic engineering,Real-time computing,Static timing analysis,Skew,CPU multiplier | Conference |
ISSN | ISBN | Citations |
1092-3152 E-ISBN : 978-1-60558-800-1 | 978-1-60558-800-1 | 31 |
PageRank | References | Authors |
2.28 | 8 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xin Zhao | 1 | 220 | 14.14 |
| Dean L. Lewis | 2 | 312 | 15.89 |
| Hsien-Hsin Sean Lee | 3 | 1657 | 102.66 |
| Sung Kyu Lim | 4 | 1688 | 168.71 |