Title
A 3 Watt 39.8–44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS
Abstract
A Dual-mode 2 ×21.5-22.3 Gb/s DQPSK or 1 × 39.8-44.6 Gb/s NRZ to 4 × 9.95-11.2 Gb/s SFI5.2-compliant two-chip SerDes for a family of 40 Gb/s optical transponders has been fabricated in 65 nm 12-metal CMOS. By demultiplexing to 16 × 2.5 Gb/s internally, all logic and testability functions could be implemented in standard-cell CMOS, resulting in total power consumption of 3 W, 75 % lower than commercial BiCMOS SFI5 40 Gb/s SerDes ICs. Chip area is 4 × 4 mm, and the ICs are flip-chip mounted into a quad flat-pack package.
Year
DOI
Venue
2010
10.1109/JSSC.2010.2057970
J. Solid-State Circuits
Keywords
Field
DocType
cmos integrated circuits,transponders,sfi5.2,limiting amplifier,deskew,flip-chip devices,voltage-controlled oscillators,voltage-controlled oscillator (vco),phase-locked loop (pll),size 65 nm,bit rate 39.8 gbit/s to 44.6 gbit/s,optical transponders,bit rate 21.5 gbit/s to 22.3 gbit/s,common-mode logic (cml),optical transponder,quadrature phase shift keying,optical communication equipment,phase locked loops,deserializer,flip-chip,serializer,serdes,dqpsk,phase interpolator,bit rate 40 gbit/s,quad flat-pack package,power 3 w,two-chip serdes,cmos,clock data recovery (cdr),chip,phase lock loop,common mode,limiting,flip chip,voltage controlled oscillator
Flip chip,BiCMOS,Computer science,Serializer,Electronic engineering,CMOS,Chip,Current-mode logic,Electrical engineering,Integrated circuit,SerDes
Journal
Volume
Issue
ISSN
45
10
0018-9200
Citations 
PageRank 
References 
11
0.85
7
Authors
23