Name
Abstract | ||
|---|---|---|
A cipher core has been implemented, which is dedicated to a 64-bit block, 128-bit key, dynamically reconfigurable hardware-based cipher, called “Chameleon”, in which two 32-cell, 8-context dynamically reconfigurable hardware units are employed to generate new subkeys for each of the 16 iterations in the encryption/decryption process. The proposed architecture has been implemented by 0.6 nm CMOS 3LM technology, using 65.6 K transistors and attaining a maximum throughput of 317.5 Mbps. The new approach demonstrates distinctive features of enhanced complexity and flexibility dedicatedly for embedded encryption/decryption applications in mobile computing |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1145/370155.370205 | Yokohama |
Keywords | Field | DocType |
decryption process,dynamically reconfigurable hardware-based cipher,cipher core,decryption application,128-bit key,cipher chip,64-bit block,8-context dynamically reconfigurable hardware,embedded encryption,new subkeys,new approach,computer architecture,embedded computing,application software,cryptography,mobile computer,throughput,hardware,mobile computing,circuits,chameleon,128 bit,information systems,chip,cmos technology | Mobile computing,Cipher,Cryptography,Computer science,Real-time computing,Encryption,Triple DES,Application software,Reconfigurable computing,Embedded system,128-bit | Conference |
ISBN | Citations | PageRank |
0-7803-6634-4 | 0 | 0.34 |
References | Authors | |
2 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yukio Mitsuyama | 1 | 134 | 20.01 |
| Zaldy Andales | 2 | 0 | 0.68 |
| Takao Onoye | 3 | 329 | 68.21 |
| Isao Shirakawa | 4 | 220 | 65.34 |