Yukio Mitsuyama - Citegraph

Author Info

Name	Affiliation	Papers
YUKIO MITSUYAMA	Kochi Univ Technol, Kochi, Japan	39
Collaborators	Citations	PageRank
68	134	20.01
Referers	Referees	References
277	375	215

Search Limit

100375

Publications (39 rows)

Collaborators (68 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Development of Autonomous Driving System based on Image Recognition using Programmable SoCs	0	0.34	2021
Measurement of Variations in FPGAs under Various Load Conditions	0	0.34	2020
33.3 Via-Switch FPGA - 65nm CMOS Implementation and Architecture Extension for Al Applications.	0	0.34	2020
Development of Autonomous Driving System Using Programmable SoCs	0	0.34	2019
Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture.	0	0.34	2018
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars.	3	0.54	2018
A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch	2	0.40	2016
Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis	0	0.34	2015
Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design And Its Irradiation Testing	3	0.54	2014
Comparative Evaluation Of Lifetime Enhancement With Fault Avoidance On Dynamically Reconfigurable Devices	0	0.34	2014
Nbti Mitigation Method By Inputting Random Scan-In Vectors In Standby Time	0	0.34	2014
Set Pulse-Width Measurement Suppressing Pulse-Width Modulation And Within-Die Process Variation Effects	0	0.34	2014
Variability and Soft-Error Resilience in Dependable VLSI Platform	0	0.34	2014
Pvt-Induced Timing Error Detection Through Replica Circuits And Time Redundancy In Reconfigurable Devices	2	0.43	2013
A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator With Stochastic Behavior Modeling	6	0.64	2013
Field Slack Assessment For Predictive Fault Avoidance On Coarse-Grained Reconfigurable Devices	0	0.34	2013
Mixed-Grained Reconfigurable Architecture Supporting Flexible Reliability And C-Based Design	0	0.34	2013
Implementing Flexible Reliability in a Coarse-Grained Reconfigurable Architecture	5	0.43	2013
Static voltage over-scaling and dynamic voltage variation tolerance with replica circuits and time redundancy in reconfigurable devices	0	0.34	2012
Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits	26	1.32	2012
Stress Probability Computation For Estimating Nbti-Induced Delay Degradation	1	0.37	2011
Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures	3	0.42	2011
NBTI mitigation by giving random scan-in vectors during standby mode	0	0.34	2011
A design procedure for oscillator-based hardware random number generator with stochastic behavior modeling	5	0.68	2010
Transistor variability modeling and its validation with ring-oscillation frequencies for body-biased subthreshold circuits	2	0.41	2010
Measurement Circuits For Acquiring Set Pulse Width Distribution With Sub-Fo1-Inverter-Delay Resolution	3	0.64	2010
Measurement circuits for acquiring SET pulsewidth distribution with sub-FO1-inverter-delay resolution	2	0.41	2010
Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits	0	0.34	2010
Coarse-grained dynamically reconfigurable architecture with flexible reliability	24	1.21	2009
An Experimental Study On Body-Biasing Layout Style Focusing On Area Efficiency And Speed Controllability	1	0.38	2009
Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits	18	1.34	2009
Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits	7	0.63	2009
Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction	12	1.11	2009
Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits	1	0.38	2008
Area-Efficient Reconfigurable Architecture For Media Processing	4	0.95	2008
Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --	1	0.37	2008
Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems	3	0.66	2005
A dynamically reconfigurable hardware-based cipher chip	0	0.34	2001
VLSI architecture of dynamically reconfigurable hardware-based cipher	0	0.34	2001