Name
Abstract | ||
|---|---|---|
We introduce a simple hierarchical design technique for building high-performance self-timed components using dynamic domino-style circuits. This technique is useful for building handshaking style functional blocks and for self-timed data path components. We wrap the dynamic domino circuit in a wrapper that communicates using a request/acknowledge protocol and mediates the pre-charge/evaluate cycle of the dynamic logic. We apply standard bundled delay matching for completion detection but add an early completion feature that can signal completion if function validity can be determined from the output value. The circuit overhead required for this early-acknowledge feature is relatively small, but can provide measurable speedup in some situations. We call this approach semi-bundled delay (SBD). |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/ISVLSI.2003.1183473 | ISVLSI |
Keywords | DocType | ISSN |
dynamic domino circuits,protocols,early completion feature,handshaking style functional blocks,hierarchical design technique,canprovide measurable speedup,dynamic domino-style circuits,dynamic logic,timing,request/acknowledge protocol,self-timed design,semi-bundled delay,dynamic domino circuit,cmos logic circuits,logic design,high-performance self-timed component,wrapper,self-timed data path components,asynchronous circuits,completion detection,thisearly-acknowledge feature,approach semi-bundled delay,dynamic domino-style circuit,self-timed data path component,bundled delay matching | Conference | 2159-3469 |
ISBN | Citations | PageRank |
0-7695-1904-0 | 3 | 0.64 |
References | Authors | |
4 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jung-Lin Yang | 1 | 7 | 2.46 |
| Erik Brunvand | 2 | 509 | 66.09 |