Name
Abstract | ||
|---|---|---|
The integration of microprocessors and field-programmable gate array (FPGA) fabric on a single chip increases both the utility and necessity of tools that automatically move software functions from the microprocessor to accelerators on the FPGA to improve performance or energy. Such hardware/software partitioning for modern FPGAs involves the problem of partitioning functions among two levels of accelerator groups - tightly-coupled accelerators that have fast single-clock-cycle memory access to the microprocessor's memory, and loosely-coupled accelerators that access memory through a bridge to avoid slowing the main clock period with their longer critical paths. This new two-level accelerator-partitioning problem was introduced, and a novel optimal dynamic programming algorithm was described to solve the problem. By making use of the size constraint imposed by FPGAs, the algorithm has what is effectively quadratic runtime complexity, running in just a few seconds for examples with up to 25 accelerators, obtaining an average performance improvement of 35% compared to a traditional single-level bus architecture |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/DATE.2007.364610 | DATE |
Keywords | Field | DocType |
longer critical path,microprocessor-accelerator partitioning,microprocessor chips,partitioning function,loosely-coupled accelerator,two-level microprocessor-accelerator partitioning,access memory,software function,accelerator group,microprocessors-field-programmable gate array integration,single-clock-cycle memory access,optimal dynamic programming algorithm,logic design,hardware-software partitioning,quadratic runtime complexity,field-programmable gate array,dynamic programming,field programmable gate arrays,average performance improvement,modern fpgas,fpga fabric,critical path,system on a chip,field programmable gate array,hardware,software performance,dynamic programming algorithm,acceleration,partition function,chip | Logic synthesis,Dynamic programming,System on a chip,Computer science,Microprocessor,Parallel computing,Field-programmable gate array,Real-time computing,Chip,Gate array,Performance improvement,Embedded system | Conference |
ISSN | ISBN | Citations |
1530-1591 | 978-3-9810801-2-4 | 7 |
PageRank | References | Authors |
0.52 | 16 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Scott Sirowy | 1 | 41 | 4.43 |
| Yonghui Wu | 2 | 1065 | 72.78 |
| Stefano Lonardi | 3 | 2940 | 175.19 |
| Frank Vahid | 4 | 2688 | 218.00 |