Paper Info
Title
Fine-Grained Run-Tume Power Gating Through Co-Optimization Of Circuit, Architecture, And System Software Design
Abstract
Power consumption has recently emerged as a first class design constraint in system LSI designs. Specially, leakage power has occupied a large part of the total power consumption. Therefore, reduction of leakage power is indispensable for efficient design of high-performance system LSIs. Since 2006, we have carried out a research project called "Innovative Power Control for Ultra Low-Power and High-Performance System LSIs", supported by Japan Science and Technology Agency as a CREST research program. One of the major objectives of this project is reducing the leakage power consumption of system LSIs by innovative power control through tight cooperation and co-optimization of circuit technology, architecture, and system software designs. In this project, we focused on power gating as a circuit technique for reducing leakage power. Temporal granularity is one of the most important issue in power gating. Thus, we have developed a series of Geysers as proof-of-concept CPUs which provide several mechanisms of fine-grained run-time power gating. In this paper, we describe their concept and design, and explain why co-optimization of different design layers are important. Then, three kinds of power gating implementations and their evaluation are presented from the view point of power saving and temporal granularity.
Year
DOI
Venue
2013
10.1587/transele.E96.C.404
IEICE TRANSACTIONS ON ELECTRONICS
Keywords
Field
DocType
low-power circuit techniques, fine grained power-gating, compiler, system hierarchy cooperation
System software,Computer architecture,Computer science,Compiler,Power gating,Circuit architecture
Journal
Volume
Issue
ISSN
E96C
4
1745-1353
Citations 
PageRank 
References 
0
0.34
10
Authors
7
Name
Order
Citations
PageRank
Hiroshi Nakamura1547.39
Weihan Wang2196.08
Yuya Ohta320.72
Kimiyoshi Usami452875.61
Hideharu Amano51375210.21
Masaaki Kondo600.34
Mitaro Namiki79720.69