| A Software-Based Nvm Emulator Supporting Read/Write Asymmetric Latencies | 0 | 0.34 | 2019 |
| A Preliminary Evaluation of Building Block Computing Systems | 0 | 0.34 | 2019 |
| Reactive NaN Repair for Applying Approximate Memory to Numerical Applications. | 0 | 0.34 | 2018 |
| Design and development of bit arrow: a web-based programming learning environment | 0 | 0.34 | 2018 |
| OpenCL Runtime for OS-Driven Task Pipelining on Heterogeneous Accelerators | 0 | 0.34 | 2018 |
| End-to-End Delay Model for Remote Surveillance over Internet and Mobile Networks | 0 | 0.34 | 2018 |
| TEE-KV: Secure Immutable Key-Value Store for Trusted Execution Environments. | 0 | 0.34 | 2018 |
| Towards write-back aware software emulator for non-volatile memory | 1 | 0.38 | 2017 |
| Building block multi-chip systems using inductive coupling through chip interface | 0 | 0.34 | 2017 |
| Building block operating system for 3D stacked computer systems with inductive coupling interconnect | 0 | 0.34 | 2017 |
| An Operating System Guided Fine-Grained Power Gating Control Based On Runtime Characteristics Of Applications | 0 | 0.34 | 2016 |
| A Fine-Grained Power Gating Control On Linux Monitoring Power Consumption Of Processor Functional Units | 1 | 0.37 | 2015 |
| Design and evaluation of fine-grained power-gating for embedded microprocessors | 4 | 0.42 | 2014 |
| First results of performance comparisons on many-core processors in solving QAP with ACO: kepler GPU versus xeon PHI | 1 | 0.39 | 2014 |
| Design of Multiple PVAS on InfiniBand Cluster System Consisting of Many-core and Multi-core | 0 | 0.34 | 2014 |
| Hardware support for resource partitioning in real-time embedded systems | 0 | 0.34 | 2013 |
| Improving Parallel I/O Performance Using Multithreaded Two-Phase I/O With Processor Affinity Management | 0 | 0.34 | 2013 |
| A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface | 2 | 0.36 | 2013 |
| Fine-Grained Run-Tume Power Gating Through Co-Optimization Of Circuit, Architecture, And System Software Design | 0 | 0.34 | 2013 |
| An efficient kernel-level blocking MPI implementation | 0 | 0.34 | 2012 |
| A design of hybrid operating system for a parallel computer with multi-core and many-core processors | 1 | 0.40 | 2012 |
| Delegation-Based MPI communications for a hybrid parallel computer with many-core architecture | 2 | 0.46 | 2012 |
| An OpenCL Runtime Library for Embedded Multi-Core Accelerator | 0 | 0.34 | 2012 |
| CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect. | 4 | 0.59 | 2012 |
| Cool Mega-Array: A highly energy efficient reconfigurable accelerator. | 8 | 0.77 | 2011 |
| Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips | 15 | 1.13 | 2011 |
| Acceleration experiment of genetic computations for sudoku solution on multi-core processors | 0 | 0.34 | 2011 |
| A Leakage Efficient Data Tlb Design For Embedded Processors | 0 | 0.34 | 2011 |
| CS unplugged assisted by digital materials for handicapped people at schools | 1 | 0.40 | 2011 |
| Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units. | 1 | 0.38 | 2011 |
| A Leakage Efficient Instruction Tlb Design For Embedded Processors | 0 | 0.34 | 2011 |
| SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator | 2 | 0.47 | 2011 |
| Proposal of a multi-core processor architecture for effective evolutionary computation | 0 | 0.34 | 2010 |
| Adaptive power gating for function units in a microprocessor | 3 | 0.54 | 2010 |
| Proposal of a multi-core processor from the viewpoint of evolutionary computation | 4 | 0.52 | 2010 |
| Reducing instruction TLB's leakage power consumption for embedded processors | 1 | 0.36 | 2010 |
| Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression | 18 | 0.92 | 2009 |
| A fine-grain dynamic sleep control scheme in MIPS R3000 | 22 | 2.04 | 2008 |
| Mobile Thin-Client System with Fault Tolerance and Scalability by "HTTP-FUSE-KNOPPIX-BOX". | 0 | 0.34 | 2007 |
| Towards Reconfigurable Cache Memory for a Multithreaded Processor | 2 | 0.42 | 2006 |
| Implementation of PC Cluster System with Memory Mapped File by Commodity OS | 1 | 0.41 | 2006 |
| A Model of Implementable SMT Processor on FPGA | 0 | 0.34 | 2006 |
| A New Model Of Reconfigurable Cache For An Smt Processor And Its Fpga Implementation | 2 | 0.46 | 2005 |
| Development Of A Thread Scheduler For Smt Processor Architecture | 1 | 0.40 | 2005 |
| Dynamic Allocation Of Physical Register Banks For An Smt Processor | 0 | 0.34 | 2004 |
| Programming in a mother tongue: philosophy, implementation, practice and effect | 0 | 0.34 | 1991 |
