Name
Abstract | ||
|---|---|---|
The embedded-DRAM testing mixes up the techniques used for DRAM testing and SRAM testing since an embedded-DRAM core combines DRAM cells with an SRAM interface (the so-called IT-SRAM architecture). In this paper we first present our test algorithm for embedded-DRAM testing. A theoretical analysis to the leakage mechanisms of a switch transistor is also provided, based on that we can test the embedded-DRAM at a higher temperature to reduce the total test time and maintain the same retention-fault coverage. The experimental results art? collected based on I-lot wafers with an 16Mb embedded DRAM core. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/TEST.2008.4700618 | 2008 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2, PROCEEDINGS |
Keywords | Field | DocType |
testing,transistors,fault coverage | Dram,Leakage (electronics),Test algorithm,Computer science,Static random-access memory,Electronic engineering,Transistor,Embedded system,Built-in self-test | Conference |
ISSN | Citations | PageRank |
1089-3539 | 3 | 0.42 |
References | Authors | |
14 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chi-Min. Chang | 1 | 15 | 2.86 |
| Mango C.-T. Chao | 2 | 48 | 7.38 |
| Rei-Fu Huang | 3 | 165 | 13.15 |
| Ding-Yuan Chen | 4 | 20 | 1.20 |