Title | ||
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Architecture design principles for the integration of synchronization interfaces into Network-on-Chip switches |
Abstract | ||
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This paper contributes to the maturity of the GALS NoC design practice by advocating for tight integration of GALS synchronization interfaces into NoC architecture building blocks. At the cost of re-engineering the input/output stages of NoC switches and network interfaces, this approach proves capable of materializing GALS NoCs with the same area and power of their synchronous counterparts, while reducing latency at the clock domain boundary. This design style is experimented in this paper with a mesochronous synchronizer and a dual-clock FIFO, which are tightly coupled with the switches of the xpipesLite NoC architecture. |
Year | DOI | Venue |
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2009 | 10.1145/1645213.1645222 | NoCArc@MICRO |
Keywords | Field | DocType |
mesochronous synchronizer,dual-clock fifo,gals synchronization interface,noc switch,materializing gals nocs,architecture design principle,clock domain boundary,xpipeslite noc architecture,gals noc design practice,noc architecture building block,design style,radiation detectors,network interface,input output,synchronisation,network on chip,computer architecture,integrated circuit design,synchronization | Synchronization,FIFO (computing and electronics),Synchronizer,Globally asynchronous locally synchronous,Computer science,Network on a chip,Real-time computing,Integrated circuit design,Throughput,Embedded system,Network interface | Conference |
ISBN | Citations | PageRank |
978-1-60558-774-5 | 7 | 0.54 |
References | Authors | |
21 | 3 |
Name | Order | Citations | PageRank |
---|---|---|---|
Daniele Ludovici | 1 | 61 | 4.92 |
Alessandro Strano | 2 | 64 | 6.67 |
Davide Bertozzi | 3 | 1653 | 99.83 |