Name
Abstract | ||
|---|---|---|
Path delay fault simulation performance on multi-cycle delay paths common in industrial designs is discussed using paths from a large block in a microprocessor and a functional test vector suite. We profile fault simulation performance using a novel ... |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/VTS.2006.87 | VTS |
Keywords | Field | DocType |
large block,profile fault simulation performance,path delay fault simulation,transition fault testing,functional test vector suite,multi-cycle delay path,industrial design,untestable defects,automatic test pattern generation,atpg,chip | Stuck-at fault,Automatic test pattern generation,Fault coverage,Computer science,Bridging (networking),Electronic engineering,Real-time computing,Reliability engineering,Test set | Conference |
ISSN | ISBN | Citations |
1093-0167 | 0-7695-2514-8 | 3 |
PageRank | References | Authors |
0.51 | 14 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xijiang Lin | 1 | 687 | 42.03 |
| Janusz Rajski | 2 | 2460 | 201.28 |