Paper Info
Title
A New Universal Test Pattern Auto-generating Approach for FPGA Logic Resources (abstract only)
Abstract
This paper presents a new universal test approach for FPGA logic resources. It includes a new greedy configuration-generating algorithm, and a new FPGA Configurable Logic Block (CLB) test model. The model is based on two directed graphs: a structure graph and a configuration graph, which convey the important information from the CLB gate level circuit to the greedy configuration-generating algorithm, so the algorithm can generate minimum the number of test configurations to achieve a given fault coverage. With this new approach, researchers can easily get test patterns optimized both in test time and fault coverage for different FPGA architectures. At the end, we compare experiment results with other test approaches, and the results show test pattern from the new approach is even more efficient than pattern from manual optimization. It also proves that the approach can deal with different types of FPGAs very well.
Year
DOI
Venue
2005
10.1145/1046192.1046228
FPGA
Keywords
Field
DocType
test approach,new universal test pattern,test model,test time,test configuration,new universal test approach,auto-generating approach,fpga logic resources,new fpga configurable logic,new approach,test pattern,new greedy configuration-generating algorithm,fault coverage,networking,reconfigurable hardware,directed graph,speculation,generic algorithm
Automatic test pattern generation,Graph,Fault coverage,Computer science,Parallel computing,Field-programmable gate array,Directed graph,Real-time computing,Configuration graph,Logic block,Reconfigurable computing
Conference
ISBN
Citations 
PageRank 
1-59593-029-9
0
0.34
References 
Authors
0
2
Name
Order
Citations
PageRank
Yirong OuYang100.34
Jiarong Tong26811.74