Name
Abstract | ||
|---|---|---|
Delay fault testing using a scan design facilitating two-pattern testing, called Chiba scan testing, requires a long test application time (TAT) compared with well-known delay fault testing. This paper presents an improved Chiba scan testing with short TAT by providing a test compaction. In addition, it presents a test generation for the Chiba scan testing improved by the proposed compaction. Evaluation shows that, for robust path delay fault testing on ISCAS89/ ADDENDUM benchmark circuits, the TAT of Chiba scan testing with the proposed compaction is, on average, 47% and 21% shorter than that of Chiba scan testing without test compaction and that of enhanced scan testing with the conventional test compaction, respectively. In addition, in many cases, the fault coverage of the proposed testing is higher than that of launch-off-capture (LoC) and launch-off-shift (LoS) testing with the same TAT. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1007/s10836-010-5177-4 | Journal of Electronic Testing |
Keywords | DocType | Volume |
Delay fault testing,Chiba scan testing,Test compaction,Test application time (TAT) | Journal | 26 |
Issue | ISSN | Citations |
6 | 0923-8174 | 1 |
PageRank | References | Authors |
0.36 | 10 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kazuteru Namba | 1 | 114 | 27.93 |
| Hideo Ito | 2 | 100 | 17.45 |