Name
Abstract | ||
|---|---|---|
In the face of large-scale process variations, statistical timing methodology has advanced significantly over the last few years, and statistical path selection takes advantage of it in at-speed testing. In deterministic path selection, the separation of path selection and test generation is known to require time consuming iteration between the two processes. This paper shows that in statistical path selection, this is not only the case, but also the quality of results can be severely degraded even after the iteration. To deal with this issue, we consider testability in the first place by integrating a satisfiability (SAT) solver, and this necessitates a new statistical path selection method. We integrate the SAT solver in a novel way that leverages the conflict analysis of modern SAT solvers, which provides more than 4X speedup without special optimizations of the SAT solver for this particular application. Our proposed method is based on a generalized path criticality metric whose properties allow efficient pruning. Our experimental results show that the proposed method achieves 47% better quality of results on average, and up to 361X speedup compared to statistical path selection followed by test generation. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/TCAD.2012.2190067 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
statistical path selection,deterministic path selection,at-speed testing,large-scale process variations,large-scale process variation,delay test,statistical analysis,testability-driven statistical path selection,generalized path criticality metric,testability,automatic test pattern generation,computability,satisfiability,statistical timing methodology,conflict analysis,statistical timing,statistical timing analysis,incremental satisfiability,sat solver,design for testability,at-speed test,test generation,path selection,better quality,new statistical path selection,testability driven statistical path selection,electronic engineering computing,time consuming iteration,process variation | Journal | 31 |
Issue | ISSN | ISBN |
8 | 0738-100x | 978-1-4503-0636-2 |
Citations | PageRank | References |
18 | 0.83 | 24 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jaeyong Chung | 1 | 77 | 10.58 |
| Xiong Jinjun | 2 | 801 | 86.79 |
| Vladimir Zolotov | 3 | 1367 | 109.07 |
| J. Abraham | 4 | 4905 | 608.16 |