Paper Info
Title
Programming Reconfigurable Decoupled Application Control Accelerator for Mobile Systems
Abstract
This paper presents an innovative multimedia reconfigurable accelerator for mobile systems associated to a programming model and a compiler flow. The architecture implements a flexible memory subsystem based on software controlled scratchpad shared memory banks. The main concern of the paper is shared memory management as it is a dominant factor in current designs and influences the performance of embedded systems as well as their energy consumption. An embedded shared-memory programming model is presented that abstracts the details of the hardware architecture but yet exposing parallelism to the user. It is open and user friendly while the hardware can execute complex data feeding on heavily pipelined datapath for compute intensive kernels. The architecture has been designed, and synthesized for 65nm technology for an operating frequency of 200MHz.
Year
DOI
Venue
2008
10.1007/978-3-540-78610-8_5
ARC
Keywords
Field
DocType
programming reconfigurable decoupled application,memory management,flexible memory subsystem,hardware architecture,memory bank,compiler flow,current design,embedded shared-memory programming model,control accelerator,mobile systems,complex data,programming model,embedded system,shared memory,embedded systems
Uniform memory access,Computer science,Real-time computing,Overlay,Datapath,Computer architecture,Shared memory,Programming paradigm,Parallel computing,Compiler,Distributed shared memory,Hardware architecture,Embedded system
Conference
Volume
ISSN
Citations 
4943
0302-9743
0
PageRank 
References 
Authors
0.34
13
3
Name
Order
Citations
PageRank
Samar Yazdani131.81
Joël Cambonie210.72
Bernard Pottier39119.77