Name
Title | ||
|---|---|---|
A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology |
Abstract | ||
|---|---|---|
In this paper an AES crypto coprocessor that is fabricated using a 0.18-μm CMOS technology is presented. This crypto coprocessor performs the AES-128 encryption in both feedback and non-feedback modes of operation. A maximum throughput of 3.84 Gbits/s is achieved at a 330 MHz clock frequency for ECB, OFB, and CBC modes of operation. This crypto coprocessor can be programmed using the memory-mapped interface of an embedded CPU core and is tested using a LEON 32-bit (SPARC V8) processor in the ThumbPod secure system-on-chip. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1145/1057661.1057677 | GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI |
Keywords | Field | DocType |
sparc v8,aes-128 encryption,cbc mode,hardware architectures,embedded cpu core,security,cryptography,thumbpod secure system-on-chip,crypto coprocessor,aes crypto coprocessor,mhz clock frequency,maximum throughput,m cmos technology,crypto-processor,fpga,vlsi,asic,advanced encryption standard aes,chip,hardware architecture,advanced encryption standard | Computer science,Field-programmable gate array,Encryption,CMOS,Application-specific integrated circuit,Coprocessor,Multi-core processor,Very-large-scale integration,Clock rate,Embedded system | Conference |
ISBN | Citations | PageRank |
1-59593-057-4 | 38 | 2.60 |
References | Authors | |
15 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alireza Hodjat | 1 | 329 | 22.91 |
| David D. Hwang | 2 | 197 | 16.02 |
| Bo-Cheng Charles Lai | 3 | 177 | 19.25 |
| Kris Tiri | 4 | 746 | 46.84 |
| Ingrid Verbauwhede | 5 | 4650 | 404.57 |