Name
Title | ||
|---|---|---|
DynaTAPP: dynamic timing analysis with partial path activation in sequential circuits |
Abstract | ||
|---|---|---|
This paper gives a method offinding all sensiti- zable paths in a non-scan ~nchronous sequential circw"t. Path activation conditions of the circuit are mapped onto a single stuck type fault by adding a few modeling gates to the netlist. Only z~ the corresponding stuck type fault is found detectable by a sequential circuit test generator is the path considered sensitizable. A depth-first analysis of circuit topology, that determines all paths between pri- mary inputs, primary outputs and flip-flops, employs a partial path hierarchy. Thus, all paths with a common unsensitizable segment need not be exam"ned separately. Results on benchwk circuits show that (1) the number of sensitizable paths can be signijlcantly smaller than that found by a static timing analyzer and (2) the partial path analysis aalls to eficiency when the number of sensitizable paths is less than 20 percent. |
Year | DOI | Venue |
|---|---|---|
1992 | 10.1109/EURDAC.1992.246252 | EURO-DAC '92 Proceedings of the conference on European design automation |
Keywords | Field | DocType |
sequential circuit,partial path activation,dynamic timing analysis,path analysis,synchronous circuit,sequential circuits,circuit topology,circuit analysis,sequential analysis,netlist,timing analysis,fault detection | Netlist,Sequential logic,Computer science,Fault detection and isolation,Real-time computing,Static timing analysis,Synchronous circuit,Network analysis,Electronic circuit,Topology (electrical circuits) | Conference |
ISBN | Citations | PageRank |
0-8186-2780-8 | 5 | 0.91 |
References | Authors | |
8 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Prathima Agrawal | 1 | 1854 | 277.08 |
| Vishwani D. Agrawal | 2 | 3502 | 470.06 |
| Sharad C. Seth | 3 | 671 | 93.61 |