Name
Abstract | ||
|---|---|---|
As processor performance continues to improve at a rate much higher than DRAM and network performance, we are approaching a time when large-scale distributed shared memory systems will have remote memory latencies measured in tens of thousands of processor cycles. The Impulse memory system architecture adds an optional level of address indirection at the memory controller. Applications can use this level of indirection to control how data is accessed and cached and thereby improve cache and bus utilization and reduce the number of memory accesses required. Previous Impulse work focuses on uniprocessor systems and relies on software to flush processor caches when necessary to ensure data coherence. In this paper, we investigate an extension of Impulse to multiprocessor systems that extends the coherence protocol to maintain data coherence without requiring software-directed cache flushing. Specifically, the multiprocessor Impulse controller can gather/scatter data across the network while its coherence protocol guarantees that each gather request gets coherent data and each scatter request updates every coherent replica in the system. Our simulation results demonstrate that the proposed system can significantly outperform conventional systems, achieving an average speedup of 9X on four memory-bound benchmarks on a 32-processor system. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1145/1138035.1138039 | TACO |
Keywords | Field | DocType |
cache coherence,memory system,scatter data,impulse memory system architecture,shadow address,shared-memory system,coherent data,remote memory,efficient address,previous impulse work,smart memory controller,multiprocessors,address remapping,32-processor system,performance evaluation,coherence protocol,data coherence,memory controller,distributed shared memory,network performance,memory latency | Uniform memory access,Shared memory,Computer science,Parallel computing,Distributed memory,Cache-only memory architecture,Real-time computing,Memory coherence,Bus sniffing,Computer hardware,Distributed shared memory,Cache coherence | Journal |
Volume | Issue | Citations |
3 | 2 | 1 |
PageRank | References | Authors |
0.34 | 20 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Lixin Zhang | 1 | 388 | 27.46 |
| Mike Parker | 2 | 1 | 0.68 |
| John B. Carter | 3 | 1785 | 162.82 |