Name
Abstract | ||
|---|---|---|
This article describes a method for reducing overall memory test time without sacrificing fault coverage. Key to this method is a test time reduction tool that helps remove redundant test items from the test flow, merge existing test patterns, and develop efficient new test patterns. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/MDT.2008.152 | IEEE Design & Test of Computers |
Keywords | Field | DocType |
overall memory test time,test flow,integrated circuit testing,existing test pattern,memory test time reduction,test patterns,redundant test items,systematic approach,efficient new test pattern,semiconductor storage,fault coverage,test time reduction tool,redundant test item,memory management,algorithm design and analysis,semiconductor memory | Automatic test pattern generation,Semiconductor memory,Flash memory,Algorithm design,Fault coverage,Computer science,Real-time computing,Memory management,Merge (version control),Test compression,Computer engineering,Reliability engineering | Journal |
Volume | Issue | ISSN |
25 | 6 | 0740-7475 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jen-Chieh Yeh | 1 | 223 | 21.72 |
| Shuo-Fen Kuo | 2 | 0 | 0.34 |
| Chao-Hsun Chen | 3 | 35 | 4.80 |
| Wu, Cheng-Wen | 4 | 1843 | 170.44 |