Name
Abstract | ||
|---|---|---|
The majority of configuration bits affecting a design are devoted to FPGA routing configuration. We present a SEU-aware routing algorithm that provides significant reduction in bridging faults caused by SEUs. Depending on the routing architecture switches, for MCNC benchmarks, the number of care bits can be reduced between 13% and 19% on average with comparable delay. In addition, in Asymmetric SRAM FPGA using our router average FIT (failure-in-time) rate is reduced by 36%. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1145/1278480.1278564 | Proceedings of the 50th Annual Design Automation Conference |
Keywords | Field | DocType |
circuit design,testing,computer science,failure analysis,network routing,reliability,soft error,field programmable gate arrays,switches,integrated circuit design,theory,routing,algorithm design and analysis,design,algorithms,computer architecture | Algorithm design,Soft error,Computer science,Bridging (networking),Field-programmable gate array,Real-time computing,Static random-access memory,Electronic engineering,Integrated circuit design,Router,Single event upset,Embedded system | Conference |
ISSN | ISBN | Citations |
0738-100X | 978-1-59593-627-1 | 17 |
PageRank | References | Authors |
0.81 | 7 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| S. Golshan | 1 | 38 | 4.10 |
| Elaheh Bozorgzadeh | 2 | 630 | 37.93 |