Paper Info
Title
Towards Virtually-Addressed Memory Hierarchies
Abstract
Abstract: Currently cache hierarchies are indexed in parallel with a TLB but their tags are part of the physical address so that the memory hierarchy is physically addressed. This design faces problems as more concurrency is exploited in the processor core and as the memory demand of emerging applications is growing fast. The traditional TLB does not scale well inside the processor core and its hit rate can be poor for data-intensive applications or scientific applications without much locality. At the same time, given current trends towards computing in memory and in communication interfaces, virtual addresses are needed not just inside the processor but throughout the memory hierarchy. These observations have prompted us to revisit the problem of moving virtual address translation away from the processor.This paper introduces new ideas to enable the use of virtual addresses throughout the memory hierarchy. The major idea is the replacement of the TLB with a small Synonym Lookaside Buffer (SLB), which scales well because its size depends on the number of synonyms, and not on the size of the application or of the physical memory. We also characterize synonym usage, evaluate the amount of cache and SLB flushing due to remapping of addresses, and compare the miss rate of various virtual/physical cache organizations for several application domains. These evaluations show that virtually-addressed memory hierarchies overall have better performance behavior than physically-addressed memory hierarchies. Finally, we also show how virtually-addressed memory hierarchies facilitate natural, scalable multiprocessor extensions, as well as computing-in-memory in the context of general-purpose computers.
Year
DOI
Venue
2001
10.1109/HPCA.2001.903251
HPCA
Keywords
Field
DocType
towards virtually-addressed memory hierarchies,physical memory,processor core,physically-addressed memory hierarchy,virtual address,virtual address translation,virtually-addressed memory,memory hierarchy,virtually-addressed memory hierarchy,memory demand,cache hierarchy,bandwidth,computer architecture,concurrent computing,application software,concurrency,sun,hardware,indexation
Interleaved memory,Uniform memory access,Physical address,Computer science,Virtual memory,Parallel computing,Real-time computing,Memory management,Non-uniform memory access,Memory map,Translation lookaside buffer
Conference
ISBN
Citations 
PageRank 
0-7695-1019-1
16
0.77
References 
Authors
21
2
Name
Order
Citations
PageRank
Xiaogang Qiu114920.35
Michel Dubois21303259.66