Name
Abstract | ||
|---|---|---|
This paper introduces a method that enables failure diagnosis of BISTed memories by compression of test responses. This method has been tested by simulation of memories with various specifications, fail patterns and test algorithms. The proposed method has been implemented in 0.18 CMOS IC. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/VTS.2001.923452 | VTS |
Keywords | Field | DocType |
cmos ic,failure diagnosis,test response compression,test algorithm,memory diagnosis,test response,bisted memory,various specification,diagnosis,hardware,bitmap,failure analysis,graphics,cmos | Compression (physics),Semiconductor memory,Test algorithm,Computer science,Electronic engineering,CMOS,Bitmap,Computer hardware,Computer memory,Built-in self-test,Embedded memory | Conference |
ISSN | Citations | PageRank |
1093-0167 | 8 | 0.79 |
References | Authors | |
0 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| John T. Chen | 1 | 24 | 1.55 |
| Wojciech Maly | 2 | 1976 | 352.57 |
| Janusz Rajski | 3 | 2460 | 201.28 |
| Omar Kebichi | 4 | 8 | 0.79 |
| Jitendra Khare | 5 | 39 | 5.41 |