Name
Abstract | ||
|---|---|---|
This paper presents a Network-on-Chip (NoC) architecture that enables the network topology to be reconfigured. The architecture thus enables a generalized System-on-Chip (SoC) platform in which the topology can be customized for the application that is currently running on the chip, including long links and direct links between IP-blocks. The configurability is inserted as a layer between routers and links, and the architecture can therefore be used in combination with existing NoC routers, making it a general architecture. The topology is configured using energy-efficient topology switches based on physical circuit-switching as found in FPGAs. The paper presents the ReNoC (ReconfigurableNoC) architecture and evaluates its potential. The evaluation design shows a 56% decrease in power consumption compared to a static 2D mesh topology |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/NOCS.2008.4492725 | NOCS |
Keywords | Field | DocType |
evaluation design,physical circuit-switching,generalized system-on-chip,direct link,mesh topology,general architecture,network topology,energy-efficient topology,long link,noc routers,network-on-chip architecture,reconfigurable topology,circuit switched,circuit topology,energy efficient,cmos technology,network on chip,energy efficiency,communication,chip,network on a chip,fpga,logic design,field programmable gate arrays,system on a chip,switches,system on chip | Logic synthesis,Logical topology,Topology,Architecture,System on a chip,Computer science,Parallel computing,Network on a chip,Field-programmable gate array,Network topology,Chip,Embedded system | Conference |
Citations | PageRank | References |
67 | 1.99 | 16 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mikkel Bystrup Stensgaard | 1 | 87 | 3.53 |
| Jens Sparsø | 2 | 453 | 52.97 |