| Synchronizing Real-Time Tasks in Time-Aware Networks: Work-in-Progress | 0 | 0.34 | 2020 |
| A Time-predictable Open-Source TTEthernet End-System | 2 | 0.45 | 2020 |
| Scratchpad Memories With Ownership | 0 | 0.34 | 2019 |
| A Time-predictable TTEthenet Node | 0 | 0.34 | 2019 |
| S4NOC: a minimalistic network-on-chip for real-time multicores | 0 | 0.34 | 2019 |
| Demonstration of a Time-predictable Flight Controller on a Multicore Processor | 0 | 0.34 | 2019 |
| Implementing Time-Triggered Communication Over A Standard Ethernet Switch | 0 | 0.34 | 2019 |
| Design and FPGA-implementation of Asynchronous Circuits Using Two-Phase Handshaking | 0 | 0.34 | 2019 |
| Hardlock: Real-time multicore locking | 0 | 0.34 | 2019 |
| Selected papers from the 2nd IEEEE Nordic Circuits and Systems Conference (NorCAS), 2016. | 0 | 0.34 | 2018 |
| A Multicore Processor for Time-Critical Applications. | 5 | 0.48 | 2018 |
| Hardware Assisted Clock Synchronization With The Ieee 1588-2008 Precision Time Protocol | 1 | 0.39 | 2018 |
| Using dynamic partial reconfiguration of FPGAs in real-Time systems. | 1 | 0.43 | 2018 |
| High-level synthesis for reduction of WCET in real-time systems | 0 | 0.34 | 2017 |
| Can real-time systems benefit from dynamic partial reconfiguration? | 1 | 0.36 | 2017 |
| Timing Organization of a Real-Time Multicore Processor | 0 | 0.34 | 2017 |
| A resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chip. | 2 | 0.46 | 2017 |
| A Controller for Dynamic Partial Reconfiguration in FPGA-Based Real-Time Systems | 4 | 0.43 | 2017 |
| Reconfiguration in FPGA-based multi-core platforms for hard real-time applications | 4 | 0.44 | 2016 |
| Avionics Applications on a Time-Predictable Chip-Multiprocessor. | 2 | 0.36 | 2016 |
| State-based Communication on Time-predictable Multicore Processors. | 0 | 0.34 | 2016 |
| Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation | 31 | 1.08 | 2016 |
| Interfacing hardware accelerators to a time-division multiplexing network-on-chip | 3 | 0.40 | 2015 |
| T-CREST: Time-predictable multi-core architecture for embedded systems | 47 | 1.62 | 2015 |
| The Argo NOC: Combining TDM and GALS | 1 | 0.35 | 2015 |
| A Time-Predictable Memory Network-on-Chip. | 14 | 0.58 | 2014 |
| Synthesis and layout of an asynchronous network-on-chip using Standard EDA tools | 2 | 0.38 | 2014 |
| Router Designs for an Asynchronous Time-Division-Multiplexed Network-on-Chip | 4 | 0.44 | 2013 |
| An area-efficient network interface for a TDM-based network-on-chip | 22 | 0.92 | 2013 |
| A Statically Scheduled Time-Division-Multiplexed Network-on-Chip for Real-Time Systems | 47 | 1.58 | 2012 |
| The ReNoC Reconfigurable Network-on-Chip: Architecture, Configuration Algorithms, and Evaluation | 7 | 0.48 | 2011 |
| Analytical derivation of traffic patterns in cache-coherent shared-memory systems | 0 | 0.34 | 2011 |
| Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend | 7 | 0.69 | 2009 |
| A Behavioral Synthesis Frontend to the Haste/TiDE Design Flow. | 9 | 0.73 | 2009 |
| Synthesis of topology configurations and deadlock free routing algorithms for ReNoC-based systems-on-chip | 4 | 0.42 | 2009 |
| ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology | 67 | 1.99 | 2008 |
| A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method | 9 | 0.63 | 2007 |
| A Low-Power Heterogeneous Multiprocessor Architecture for Audio Signal Processing | 5 | 0.79 | 2004 |
| Future directions in clocking multi-ghz systems | 1 | 0.59 | 2002 |
| Designing asynchronous circuits for low power: an IFIR filter bank for a digital hearing aid | 45 | 3.63 | 1999 |
| Design of Self-timed Multipliers: A Comparison | 14 | 4.76 | 1993 |
| Delay-insensitive multi-ring structures | 50 | 18.46 | 1993 |
| Design of delay insensitive circuits using multi-ring structures | 39 | 3.53 | 1992 |
| Design Of A Fully Parallel Viterbi Decoder | 3 | 0.71 | 1991 |
