Name
Title | ||
|---|---|---|
Power Gating Implementation For Supply Noise Mitigation With Body-Tied Triple-Well Structure |
Abstract | ||
|---|---|---|
This paper investigates power gating implementations that mitigate power supply noise. We focus on the body connection of power-gated circuits, and examine the amount of power supply noise induced by power-on rush current and the contribution of a power-gated circuit as a decoupling capacitance during the sleep mode. To figure out the best implementation, we designed and fabricated a test chip in 65 nm process. Experimental results with measurement and simulation reveal that the power-gated circuit with body-tied structure in triple-well is the best implementation from the following three points; power supply noise due to rush current, the contribution of decoupling capacitance during the sleep mode and the leakage reduction thanks to power gating. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1587/transfun.E95.A.2220 | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES |
Keywords | Field | DocType |
power gating, on-chip power supply noise, rush current, well structure | Monad (category theory),Noise control,Power gating,Electrical engineering,Mathematics | Journal |
Volume | Issue | ISSN |
E95A | 12 | 0916-8508 |
Citations | PageRank | References |
0 | 0.34 | 6 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yasumichi Takai | 1 | 0 | 0.34 |
| Masanori Hashimoto | 2 | 462 | 79.39 |
| Takao Onoye | 3 | 329 | 68.21 |