Name
Abstract | ||
|---|---|---|
A graph-based technology mapping algorithm, called DAG-Map, for delay optimization in lookup-table-based field programmable gate array (FPGA) designs is presented. The algorithm carries out technology mapping and delay optimization on the entire Boolean network, instead of decomposing it into fanout-free trees and mapping each tree separately as in most previous algorithms. As a preprocessing step, a general algorithm that transforms an arbitrary n-input network into a two-input network with only O(1) factor increase in the network depth is introduced. Also presented is a graph-matching-based technique used as a postprocessing step which optimizes the area without increasing the delay. The DAG-Map algorithm was tested on the MCNC logic synthesis benchmarks. Compared with previous algorithms, it reduces both the network depth and the number of lookup-tables |
Year | DOI | Venue |
|---|---|---|
1992 | 10.1109/ICCD.1992.276239 | Cambridge, MA |
Keywords | Field | DocType |
delay optimization,improved graph-based fpga techology,mapping algorithm,network synthesis,design optimization,logic design,boolean functions,logic gates,graph matching,tree graphs,field programmable gate arrays,logic synthesis,generic algorithm,boolean network,field programmable gate array,lookup table | Boolean function,Logic synthesis,Boolean network,Logic gate,Tree (graph theory),Computer science,Network synthesis filters,Parallel computing,Field-programmable gate array,Algorithm,Preprocessor | Conference |
ISBN | Citations | PageRank |
0-8186-3110-4 | 7 | 0.66 |
References | Authors | |
0 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jason Cong | 1 | 7069 | 515.06 |
| Yuzheng Ding | 2 | 239 | 19.46 |
| Andrew B. Kahng | 3 | 7582 | 859.06 |
| Peter Trajmar | 4 | 35 | 2.95 |
| Kuang-chien Chen | 5 | 347 | 30.84 |